1. Field of the Invention
The invention relates to a circuit configuration for dividing a clock signal with switchable or reversible divider ratios of 4/5 by emitter coupled logic, having three series-connected flip-flops, wherein a positive output of one flip-flop is coupled to a data input of a respective downstream flip-flop, and clock inputs of the flip-flops are acted upon by the clock signal.
In the development of cellular or cordless telephones, the present goal is a 2.7 V supply voltage. It is therefore necessary to make available bipolar predividers with low current consumption for that supply voltage. That leads to problems in particular in achieving the required rapid synchronized 4/5 divider.
One such divider circuit configuration is known, for instance, from the "SP8000 Series High Speed Dividers Integrated Circuit Handbook" issued by Plessey Semiconductors, pp. 113 ff. A divider component SP8690A&B is made by emitter coupled logic (ECL) and requires a supply voltage of 5 V. The divider is constructed as a three-stage Johnson counter shown in FIG. 2 of the aforementioned handbook. In the case of the 2.7 V ECL circuitry, the gates can no longer be constructed in such a way that their transit time is eliminated. In other words, the transit times of the gates that precede the flip-flops add together and lead to a reduction in the upper limit frequencies.
2. Summary of the Invention
It is accordingly an object of the invention to provide a circuit configuration made by ECL which enables a divider circuit configuration with a high limit frequency and a low supply voltage to be provided and which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration being made by differential technology for dividing a clock signal with switchable divider ratios of 4/5 by emitter coupled logic, comprising first, second and third series-connected flip-flops each having an output, a data input and a clock input, the output of the second flip-flop being coupled to the data input of the third flip-flop, and the clock inputs of the first, second and third flip-flops being acted upon by a clock signal; a first AND gate being connected upstream of the first flip-flop and having a first input being acted upon by a control signal for switching over the divider ratio, and a second input being acted upon by an inverted signal from the output of the third flip-flop; a second AND gate being connected between the first and second flip-flops and having an output connected to the data input of the second flip-flop, a first input receiving an inverted signal from the output of the first flip-flop, and a second input being acted upon by the inverted signal from the output of the third flip-flop.
In accordance with another feature of the invention, there are provided n divider stages (n.ltoreq.1) each having a flip-flop and an OR stage including first and last flip-flops and first and last OR stages; each of the flip-flops of the divider stages except the last flip-flop having an inverted output, each of the flip-flops of the divider stages having a clock input, and each of the OR stages having a first input, a second input and an output; the flip-flops of the divider stages being connected in series with the output of the third flip-flop, with the inverted outputs of each of the third flip-flop and the flip-flops of the divider stages each being connected to the clock input of a respective one of the flip-flops being connected downstream; the n series-connected OR gates being connected upstream of the first input of the first AND gate, with the first input of each of the OR gates except for the first OR gate each being acted upon by an output signal from the output of a respective one of the OR gate being connected upstream, the second input of each of the OR gates except for the first OR gate receiving an inverted output signal from the inverted output of a respective one of the flip-flops of the divider stages, the first input of the first OR gate receiving a control signal, and the output of the last OR gate being connected to the first input of the first AND gate.
In accordance with a concomitant feature of the invention, there is provided a multiplexer receiving at least two output signals of two of the series-connected flip-flops and having an output at which a divided clock signal can be picked up.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit configuration for dividing a clock signal, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.